I am writing verilog code for 4 bit adder subtractor. I am using structural design. At first I have written verilog code for 1 bit full adder. Then I am using that to write code for 4 bit adder subtractor .
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B,. Jan 26, 2013 - FULL ADDER. Module fa(a, b, c, sum, carry). Output carry.
Subhadip
SubhadipSubhadip
2 Answers
You're actually pretty close. What you seem to not understand is that in Verilog your design is synthesized at compile time, not at run time. You can't instantiate modules conditionally because at compile time we don't know if that condition will be met or not. So your first statement in the case of the subtraction bit being low doesn't really make sense. It also doesn't make sense to put it in an always block, since the rtl is defined in the modules already.
However, your second statement contains most of the solution to the problem. When the sign bit is low, those xors at the top of the adder/subtractor will preserve the incoming bits, and the design will simplify to just an adder. Try just using the second block alone.
dustinwerrandustinwerran
Make use of complimenting B using XOR gate (when in=1) before putting into the values in the instantiated modules.
when the in=0, same B will be added to A and when in=1, ~B will be added to A.
Amritanjan KumarAmritanjan Kumar
Not the answer you're looking for? Browse other questions tagged veriloghdliverilog or ask your own question.